The present invention relates to semiconductor processing, and in particular, adaptive processing to minimize the effect of wafer and processing variations in the final semiconductor circuit.
Natural variations in materials and processing steps cause variations in performance of semiconductor devices. These variations may change drastically from wafer to wafer and lot to lot. In the case of amplifier circuitry incorporating heterojunction bipolar transistors (HBT) formed using a gallium arsenide process, there is significant variation in final circuit performance based on the variations in manufacturing materials. In particular, large variations in beta for each HBT device requires designers to work with similar variations in idle current, gain, power, efficiency and other key parameters bearing directly on performance. Further, large variations in beta result in low manufacturing yields because these variations in beta are often outside of the already excessive tolerances taken into consideration in the circuit design. As such, there is a need for a way to improve manufacturing yields and to compensate for process variations in a cost-effective and time-efficient manner.
The present invention provides an adaptive manufacturing technique for measuring device parameters at a point in the manufacturing process and for making adjustments during processing to compensate for variation in these parameters. The preferred process reduces the performance variation resulting from variation in transistor beta in power amplifier circuits made from hetero-junction bipolar transistors (HBT).
The process involves using beta values, determined by on-wafer testing at a midpoint in the fabrication process. Typically, testing is done after application of the first interconnect metal layer. The beta value determined from the testing is used to select connection points to a series of resistors used to control the bias currents driving the HBT amplifier circuit. Appropriate connections are made in a subsequent metal layer and optimize bias conditions in the final circuit by compensating for variations in beta. The given device beta and selected bias resistance effectively trims the quiescent current settings and results in much tighter performance tolerances for the final device. Compensating for variations in beta significantly reduces variations in idle current, gain, power, efficiency and other key parameters bearing directly on device performance.